The present invention generally relates to a method of manufacturing a semiconductor device. In particular, the invention is concerned with a semiconductor device manufacturing method which makes it possible to form a wiring layer having a large current capacity in a facilitated manner.
In accompaniment to the tendency of the semiconductor device being implemented with more and more increasing integration density, dimensions of wiring conductors or layers realized in the semiconductor device tend to become extremely reduced. Additionally, a so-called multi-layer wiring technique is increasingly adopted in which a plurality of wiring layers are stacked in a laminated structure with an insulation film being interposed between the adjacent wiring layers.
Use of the fine wiring conductors or layers and the multi-layer wiring structure in the semiconductor device is however accompanied with several problems.
For having a better understanding of the background of the invention, discussion will be made in some detail by referring to FIG. 1 of the accompanying drawings on the problems which the hitherto known wiring technique suffers. FIG. 1 shows a typical one of the conventional wiring structures such as disclosed, for example, in "Technical Digest of IEDM", (1983), p.p. 550 to 553. Referring to the figure, a silicon substrate 10 has formed thereon a lower wiring layer 11 formed, for example, of an Al-Si alloy on which a SiO.sub.2 -film 12 is formed as an inter-layer insulation film. The SiO.sub.2 -film 12 has a contact hole 13 formed therethrough at a predetermined position. The contact hole 13 is filled with tungsten (W) as denoted by a numeral 14 through a selective vapor growth process. The tungsten contact 14 burried in the contact hole 13 exhibits a high allowable current density and is effective for enhancing the reliability. An upper wiring layer 15 is additionally formed on the inter-layer insulation film 12, whereby a multi-layer wiring structure is realized.
Although the metal 14 filling the contact hole 13 in the hitherto known wiring structure can ensure an enhanced reliability as mentioned above, it is noticed that the allowable current density at contact regions 13a and 13b located between the metal body 14 filling the contact hole 13 and the upper wiring layer 15 and the lower wiring layer 11, respectively, is limited by the allowable current density of the materials which constitute the upper and lower wiring layers. As a consequence, the metal such as W deposited in the contact hole 13 can not necessarily lead to the improvement of realiability of the wiring, giving rise to a problem.